AN1279

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AN1279 - AN1279

AN1279
Offline Reference Design Using dsPIC®
Authors: Sagar Khare Mohammad Kamil Microchip Technology Inc.
Types Systems
typical computers four basic protection roles: being able cope with power surges, voltage shortage, complete power failure wide variations electric current frequency. There three types systems, depending electric power being stored relayed electronic device connected them: Offline (also known Standby UPS) Line-Interactive Continuous UPS) Online (often called double conversion supply)
OVERVIEW
Uninterruptible Power Supply, UPS, electronic device that provides alternative electric power supply connected electronic equipment when primary power source available. Unlike auxiliary power, provide instant power connected equipment, which protect sensitive electronic devices allowing them shut down properly preventing extensive physical damage. However, only supply energy limited amount time, typically minutes. Although extend virtually unlimited list applications, past years become even more popular means protecting computers telecommunication equipment, thus preventing serious hardware damage data loss.
OFFLINE
Offline system (see Figure redirects electric energy received from input load only switches providing power from battery when problem detected utility power. Performing this action usually takes milliseconds, during which time power inverter starts supplying electric energy from battery load.
Application Markets Systems
systems provide large number applications variety industries. Their common applications range from small power rating personal computer systems medium power rating medical facilities, life-support systems, data storage, emergency equipment, high power rating telecommunications, industrial processing, online management systems. Different considerations should taken into account these applications. example, emergency systems lighting support system 90-120 minutes. other applications like computer backup power, typically support system 15-20 minutes. power restored during that time, system will gracefully shut down. longer backup period considered, larger battery required. process equipment high power applications, some systems designed provide enough time secondary power sources, such diesel generators, start
FIGURE
Input
OFFLINE DIAGRAM
Load
Inverter Charger
Battery
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LINE-INTERACTIVE
Line-Interactive (see Figure always relays electric energy through battery load. When mains power available, battery being charged continuously. same time, regulates output voltage related coupling inverter nearly zero. When power outage occurs, transfer switch opens electric energy flows from battery load (Stored Energy mode). these characteristics, continuous systems tend somewhat more expensive than offline UPS.
FIGURE
ONLINE DIAGRAM
Static Switch (Static Bypass)
Input Rectifier/ Charger Battery Inverter
Load
FIGURE
LINE-INTERACTIVE DIAGRAM
Static Switch
Input
Load
SYSTEM SPECIFICATIONS
reference design this application note describes design Offline Uninterruptible Power Supply (UPS) using Switch Mode Power Supply (SMPS) dsPIC® Digital Signal Controller (DSC). Offline Reference Design consists three major topology blocks: Push-Pull Converter (steps battery voltage constant high-voltage Full-Bridge Inverter (converts voltage sinusoidal output) Flyback Switch Mode Charger (current source charges battery with constant current) input output specifications shown Table
Inverter
Legend:
Battery Normal mode Stored-energy mode
ONLINE
Online (see Figure combines basic technologies previously described models, with rectifiers inverter systems working time. case with Line-Interactive UPS, power transfer made instantly outage occurs, with rectifier simply being turned while inverter draws power from battery. utility power again established, inverter continues supply power connected devices, while rectifier resumes activity, recharging battery. This design sometimes fitted with additional transfer switch bypass during malfunction overload.
TABLE
Input Input Output Rating Input Filtering Input Input Output Rating Input Filtering
SPECIFICATIONS
±10%, (lead acid battery) VAC, sinusoidal 1000 W/1000 (1300VA seconds) EMI/RFI filtering ±10%, (lead acid battery) VAC, sinusoidal 1000 W/1000 (1300VA seconds) EMI/RFI filtering 110V Specifications
220V Version Specifications
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OFFLINE REFERENCE DESIGN
Offline system shown Figure operates Standby mode mode. When line voltage present, system Standby mode until failure occurs line. During Standby mode, battery charged maintained after becoming fully charged. When battery charging, inverter works rectifier through IGBT's anti-parallel diodes. flyback switch mode charger acts current generator provides constant charging current battery. After power failure, system switched mode. this situation, DPDT relay turned prevent power from being delivered line. push-pull converter steps battery voltage VDC. high voltage then converted with full-bridge inverter filtered with filter create pure sine wave 220/110 output where load connected. This power switchover sequence made less than
FIGURE
OFFLINE REFERENCE DESIGN
VAC,
Filter
DPDT Relay
Load
Constant Current
Flyback Switch Mode Charger
Filter
Battery
Push-Pull DC/DC Converter
Full-Bridge Inverter/ Rectifier
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Listing Signals Each Block, Type Signal, Expected Signal Levels
PUSH-PULL CONVERTER
specified Figure measurement output voltage (UDCM) required implement control algorithm. signal enabling driver, temperature sensor measures heat sink temperature, primary current measurement (IP) protects converter case transformer flux walking. outputs from dsPIC firing pulses driver control output voltage.
FIGURE
PUSH-PULL CONVERTER RESOURCE DIAGRAM
UDCM+
UBAT
PGND
UDCM-
UCDM
Temperature Sensor
DRIVER
dsPIC33FJ16GS504
Table lists resources used dsPIC device push-pull converter.
TABLE
RESOURCES REQUIRED DIGITAL PUSH-PULL CONVERTER
Type Signal Analog Analog Analog Analog Enable driver, Digital Digital dsPIC® Resources Used PWM3H, PWM3L Expected Signal Level 2.99V 0V-1.65V 0V-3.3V 1.5V-1.98V
Signal Name UDCM (optional, implemented software) Push-Pull Gate Drive
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FULL-BRIDGE INVERTER
block diagram Figure illustrates that measurement output voltage (ACO) required implement control algorithm. With measurement output current (I), that current limited prevent overloading converter. presence power grid voltage detected with measurement (ACI) voltage. When power grid voltage fails, signal turns relay prevents power flow line when operational. Signal controls relay, which when link voltage prevent current inrush link capacitors when power grid voltage rectifier. This happens when operational battery depleted, goes initial system connect grid power. FLT_CLR signal used reset driver when fault detected. FAULT/SD SYS_FLT used enable disable driver detect driver faults. Detailed descriptions these signals found data sheet drivers (IR2214). Switching inverter IGBTs controlled firing pulses generated dsPIC modules.
FIGURE
UDC+
DIGITAL FULL-BRIDGE INVERTER RESOURCE DIAGRAM
(Inverter Series Relay) DRIVER FLT_CLR FAULT/SD SYS_FLT (Mains Relay) ACI1M Power Grid ACI2M
PGND
FLT_CLR FAULT/SD SYS_FLT
ACO1M Load ACO2M
DRIVER
KF(1)
dsPIC33FJ16GS504
KG(1)
Note
feedback gain circuits. Refer Appendix "Schematics Board Layout" details.
Table shows resources used dsPIC device full-bridge inverter.
TABLE
RESOURCES REQUIRED DIGITAL FULL-BRIDGE INVERTER
Type Signal Analog Analog Analog Digital output Digital output Digital output Digital input (external interrupt) Digital input output output dsPIC® Resources Used AN11 RC10 RC13 (INT1) PWM1H, PWM1L PWM2H, PWM2L Expected Signal Level 0.27V-3.3V 0.15V-3.16V 2.5V (nominal)
Signal Name FLT_CLR FAULT/SD SYS_FLT (gate drive) (gate drive)
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FLYBACK SWITCH MODE CHARGER
block diagram Figure shows that analog current controller used battery charging. Four signals needed: signal enabling topswitch, (IB) measuring battery charging current, (UB) measuring battery voltage IREF reference with PWM4L output.
FIGURE
UDC+
DIGITAL FLYBACK SWITCH MODE CHARGER RESOURCE DIAGRAM
Shunt UBAT
K3(1) PGND Flyback transformer UFEEDBACK K4(1) TOPSWITCH ENABLE
PGND
+15V
IERROR
IFEEDBACK IREF
dsPIC33FJ16GS504
Analog Controller
Note
feedback gain circuits. Refer Appendix "Schematics Board Layout" details.
Table shows resources used dsPIC device flyback switch mode charger.
TABLE
RESOURCES REQUIRED DIGITAL FLYBACK SWITCH MODE CHARGER
Type Signal Analog Analog Digital output output dsPIC® Resources Used PWM4L Expected Signal Level 0V-1.67V 1.5V-2V
Signal Name IBAUBAT IREF
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DC/DC CONVERTER
Most designs contain transformer-type DC/DC converter. transformer provides electrical isolation between input output converter. transformer also provides option produce multiple voltage levels changing turns ratio, provide multiple voltages using multiple secondary windings. Transformer-type DC/DC converters divided into five basic topologies: Forward Converter Push-Pull Converter Half-Bridge Converter Full-Bridge Converter Flyback Converter Selection topology depends careful analysis design specifications, cost size requirements converter. Operation each above topologies described following sections this application note. Details topology selection hardware design provided subsequent sections.
Forward Converter
forward converter, which step-up stepdown converter, shown Figure When transistor appears across primary, then generates output voltage determined Equation diode secondary ensures that only positive voltages applied output circuit while provides circulating path inductor current transformer voltage zero negative. third winding added transformer forward converter, also known "reset winding". This winding ensures that magnetization transformer core reset zero start switch conduction. This winding prevents saturation transformer.
Flyback topology operation differs slightly from other topologies that energy stored magnetic material then released. Other topologies always transfer energy directly from input output. Another case which topologies distinguished from each other transformer core utilization: Unidirectional core excitation where only positive part (quadrant loop used (flyback forward converters) Bidirectional core excitation where both positive (quadrant negative (quadrant parts loop utilized alternatively (push-pull, half-bridge, full-bridge converters)
FIGURE
FORWARD CONVERTER
VOUT
EQUATION
Vout
where duty cycle transistor
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Push-Pull Converter
push-pull converter shown Figure When switches current flows through upper half transformer primary magnetic field expands. expanding magnetic field induces voltage across secondary; polarity such that forward-biased reverse-biased. conducts charges output capacitor form filter network. When turns OFF, magnetic field collapses after period dead time (dependent duty cycle drive signal), conducts, current flows through lower half T1's primary, magnetic field expands. this point, direction magnetic flux opposite that produced when conducted. expanding magnetic field induces voltage across secondary; polarity such that forward-biased reverse-biased. conducts charges output capacitor After period dead time, conducts cycle repeats.
FIGURE
PUSH-PULL CONVERTER
VOUT
There important considerations with push-pull converter: Both transistors must conduct together, this would effectively short circuit supply. This means that conduction time each transistor must exceed half total period 0.5) complete cycle, otherwise conduction will overlap. magnetic behavior circuit must uniform; otherwise, transformer saturate, this would cause destruction This behavior requires that individual conduction times must exactly equal halves center-tapped transformer primary must magnetically identical. These criteria must satisfied control drive circuit transformer. output voltage equals that Equation
EQUATION
Vout
where: duty cycle transistors N2/N1 secondary-to-primary turns ratio transformer
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Half-Bridge Converter
half-bridge converter (see Figure similar push-pull converter, center-tapped primary required. reversal magnetic field achieved reversing direction primary winding current flow. this case, capacitors. required form input mid-point. Transistors turned alternately avoid supply short circuit, which case duty cycle, must less than 0.5. half-bridge converter, output voltage VOUT equals that Equation
FIGURE
HALF-BRIDGE CONVERTER
+VIN
+VOUT
EQUATION
Vout
where: duty cycle transistors N2/N1 secondary-to-primary turns ratio transformer
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Full-Bridge Converter
full-bridge converter topology shown Figure basically same half-bridge converter, where four transistors used. Diagonal pairs transistors (Q1-Q4 Q2-Q3) conduct alternately, thus achieving current reversal transformer primary. Output voltage equals that Equation
FIGURE
FULL-BRIDGE CONVERTER
+VIN
+VOUT
EQUATION
Flyback Converter
Vout
where: duty cycle transistors N2/N1 secondary-to-primary turns ratio transformer
Figure shows flyback converter circuit. When transistor winding polarities, diode becomes reverse-biased. Therefore, transformer core flux increases linearly. When transistor turned OFF, energy stored core causes current flow secondary winding through diode flux decreases linearly. Output voltage given Equation
FIGURE
+VIN
FLYBACK CONVERTER
+VOUT
EQUATION
Vout
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VOLTAGE SOURCE INVERTER (VSI)
single-phase Voltage Source Inverter (VSI) defined half-bridge full-bridge topology. Both topologies widely used power supplies single-phase systems.
Full-Bridge
Figure shows topology Full-Bridge VSI. This inverter similar half-bridge inverter; however, second provides neutral point load. Both switches S2-) cannot simultaneously because short circuit across link voltage source would produced. avoid short circuit across undefined output voltage condition, modulating technique should ensure that either bottom switch each instant. output voltage take values link value which twice value obtained with half-bridge topologies. Several modulating techniques have been developed that applicable full-bridge VSIs. Among them, best known bipolar unipolar techniques.
Half-Bridge
Figure shows topology Half-Bridge VSI, where large capacitors required provide neutral point such that each capacitor maintains constant voltage Because current harmonics injected operation inverter low-order harmonics, large capacitors required. duty cycle switches used modulate output voltage. signals driving switches must ensure some dead time prevent shorting bus.
FIGURE
SINGLE-PHASE HALF-BRIDGE
CSD-
FIGURE
SINGLE-PHASE FULL-BRIDGE
S1D1S2b
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BATTERY CHARGER
When mains voltage present, Offline charges batteries, therefore, battery charger circuit implemented. Most battery chargers divided into four basic design types, topologies: Linear Chargers Switch Mode Chargers Ferroresonant Chargers Chargers battery, rectifier that smooths existing sinusoidal signal into constant-voltage signal. linear regulating element passive component such resistor active component such transistor that controlled reference signal. Figure shows simplified schematic linear charger with linear power supply with resistor current regulating element.
Switch Mode Chargers
switch mode charger, voltage rectified, then converted lower voltage through DC/DC converter. This type charger contains additional charge control circuitry regulate current flow into battery. charge control regulates which power switch turns OFF, accomplished through circuit, specialized integrated chip, some type software control. simplified schematic single piece switch mode charger shown Figure
Linear Chargers
Linear chargers consist power supply, which converts power lower voltage power, linear regulating element, which limits current that flows into battery. power supply typically consists transformer that steps down power from 220/110 lower voltage closer that
FIGURE
LINEAR CHARGER
Transformer Rectifier Current Regulating Element Battery
Input Output
Power Supply
Charge Control
FIGURE
SWITCH MODE CHARGER
Rectifier Power Switch Transformer Output Filter Battery
Input Output
Power Supply Current Control Logic
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Ferroresonant Chargers
Ferroresonant chargers (sometimes called ferro chargers), operate special component called ferroresonant transformer. ferroresonant transformer reduces voltage lower regulated voltage level while simultaneously controlling charge current. rectifier then converts power power suitable battery. Figure shows block diagram ferroresonant charger.
Chargers
chargers special component known Silicon-Controlled Rectifier (SCR) control current battery. controllable switch that turned multiple times second. After transformer reduces utility voltage value near that battery, diodes rectify current while enables flow charge current according control signal. block diagram charger shown Figure
FIGURE
FERRORESONANT CHARGER
Ferroresonant Transformer Rectifier Battery Charge Control
Input
Output
Power Supply
FIGURE
CHARGER
Diode Rectifier Current Limiter
Transformer
Battery
Input Output
Power Supply
Charge Control
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SOFTWARE DESIGN
Offline Reference Design controlled single dsPIC device shown system block diagram Figure
FIGURE
OFFLINE BLOCK DIAGRAM
Power Conversion Block Push-Pull Converter Full Bridge Voltage-Source Inverter Output
Load
3x12V Batteries
Relay Logic
Auxiliary Power Supply
Flyback Battery Charger
Mains Input Rectified Inverter Body Diodes
dsPIC®
Controller PIC18F2420
Controller PIC18F2450
Module
Port
Legend: Signal Flow Power Flow
User Interface Block
Computer
dsPIC device heart Offline UPS. controls critical operations system well housekeeping operations. functions dsPIC broadly classified into following categories: power conversion algorithms state machine different modes operation Auxiliary tasks including true calculations, soft start routines user interface routines. dsPIC device offers "intelligent power peripherals" specifically designed power conversion applications. These intelligent power Peripherals include High-Speed PWM, High-Speed 10-bit ADC, High-Speed Analog Comparator modules.
These peripheral modules include features that ease control switch-mode power supply with high resolution PWM, flexible triggering, comparator fault handling. addition intelligent power peripherals, dsPIC also provides built-in peripherals digital communications including I2CTM, UART that used power management housekeeping functions. Note: device details, refer dsPIC33F "GS" series device data sheets. more information peripherals, refer corresponding SMPS sections "dsPIC33F Family Reference Manual".
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high-level diagram Offline software structure shown Figure shown this figure, software broadly partitioned into parts: State Machine (includes power conversion routines) User Interface Software These partitions described more detail subsequent sections this document.
FIGURE
OFFLINE SOFTWARE: HIGH-LEVEL PARTITIONS Offline Software
State Machine (Interrupt Based) Priority: Medium Execution Rate: Medium Power Conversion Algorithms (Interrupt Based) Priority: Execution Rate: User Interface Software
Priority: High Execution Rate: High
State Machine
Offline software implements state machine determine mode operation system. state machine executed once every inside timer Interrupt Service Routine (ISR). state machine configures on-chip peripherals execute correct power conversion algorithms. During normal operation offline UPS, state machine configures system peripherals execute correct power conversion algorithms determined system state. When power failure occurs, state machine initiates switchover sequence from Battery Charger mode Inverter mode. When mains detected again, state machine executes switchover from Inverter mode Battery Charger mode. These switchover functions must executed little time possible ensure uninterrupted power load. Battery Charger mode Inverter mode normal operating modes Offline UPS. There other modes operation, namely System Startup System Error. Each mode operation Offline described following sections. Figure shows Offline state diagram.
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FIGURE OFFLINE STATE DIAGRAM
System Startup
C_LI
MAINS_OK DC_LINK_OK (BATTERY_OK BATTERY_LOW)
MAINS_NOT_OK DC_LINK_OK BATTERY_OK
MAINS_OK DC_LINK_UNDERVOLTAGE
BATTERY_OVERVOLTAGE
MAINS_OK DC_LINK_OVERVOLTAGE
MAINS_NOT_OK
C_LI _LINS_O
Battery Charger Mode
Inverter Mode
S_NOT LINK_
System Error
MAERY
LINK
BATTERY_OVERVOLTAGE
System Startup
When Offline turned state system unknown. Therefore, state machine first monitors system variables determines starting state UPS. During this time, state machine also monitors fault conditions ensures that system variables within specification that switch normal operation.
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BATTERY CHARGER MODE
mains voltage detected, Inverter mode disabled running) Offline switches Battery Charger mode. dsPIC device provides reference current level with variable duty cycle signal. battery voltage measured ascertain state battery. Depending battery state, value charging current modified achieve fastest charging time also prolong life batteries. battery charging profile been configured sealed lead-acid (SLA) batteries, summarized Figure battery charger control implemented partly hardware partly software. flyback converter used produce constant current source from rectified mains voltage. dsPIC device provides reference signal output current flyback converter. This current reference signal generated filtering output from dsPIC DSC. charging current controlled modifying duty cycle current reference signal. When Battery Charger mode started, dsPIC device sets minimum charging current. Then, battery voltage battery current measured using high-speed 10-bit module. measured battery voltage determines charging state, code specifies correct charging current from battery charging profile shown Figure system variables monitored state machine initiate switchover sequence required. When mains power failure detected, state machine switches operation Inverter mode. fault detected, system state changed System Error.
FIGURE
OFFLINE BATTERY CHARGING PROFILE
Charging Current 2.25A Charging Trickle Charging State Bulk Charging State Over Charging State Float Charging State Charging
0.1A
35.7V
40.5V
43.2V
Battery Voltage
Note: drawn scale
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BATTERY CHARGER INITIALIZATION ROUTINE
When offline switches Battery Charger mode, code must ensure that previous mode turned OFF. reduce stress hardware components, full-bridge inverter turned when output reaches flowchart Battery Charger mode shown Figure After inverter turned OFF, output relay released that mains connected output. output relay must released shortest possible duration that there interruption power output. Typically, relay switching times limiting factor switchover duration.
FIGURE
BATTERY CHARGER INITIALIZATION FLOWCHART
State Machine Push-Pull Control Loop (ADC Interrupt) Battery Charger Initialization Priority: Medium
System Startup Inverter Mode
Priority: High
Relay flag NOT_READY_TO_SWITCH
Inverter Control Loop (ADC Interrupt)
relay ready switch? (Relay flag cleared ISR)
Priority: High
Initiate relay release Call delay allow inverter output become Turn inverter signals
Battery Voltage Current Measurement (ADC Interrupt)
Bypass link charging resistor
Priority: Medium
Call delay allow complete release relay Reset charging state UNKNOWN minimum charging current reference Enable charging current reference signal (PWM4L) Enable Battery Charger Flyback Converter
Mains Detection (ADC Interrupt)
Priority: Medium
Battery Charger Mode
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dsPIC device implements predictive technique achieve fastest switchover time possible. This done predicting relay switching time initiating relay release even before inverter output turned OFF. switchover operation from inverter mains described subsequent sections this application note. battery charging current control scheme illustrated Figure battery charger control routine called inside state machine under Battery Charger mode. battery charging control loop therefore executed same rate (once every also same priority level state machine. battery current voltage measurement triggered using trigger feature dsPIC device. measured data scaled stored variable data memory asynchronous control loop execution. When control loop called, data simply read from data memory used control loop calculations. flowchart battery charger control loop shown Figure
BATTERY CHARGER CONTROL SCHEME
battery charger control loop implemented state machine. measured charging current less than reference, duty cycle incremented fixed step. Conversely, charging current exceeds reference, duty cycle reduced same fixed step. This process continues until current error reduces negligible value.
FIGURE
BATTERY CHARGER CONTROL SCHEME
Quantizer
Duty Cycle
Charging Current Reference Measured Charging Current
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FIGURE BATTERY CHARGER MODE FLOWCHART
State Machine Push-pull control loop (ADC Interrupt) Battery Charger Control Loop Priority: Medium
Battery Charger Mode
Priority: High
battery voltage BATTERY_TRICKLE_VOLTAGE?
Inverter control loop (ADC Interrupt)
battery voltage BATTERY_BULK_VOLTAGE?
Priority: High
Maximum Charging Current
Battery Voltage Current Measurement (ADC Interrupt)
battery voltage BATTERY_FLOAT_VOLTAGE?
Calculate Charging Current
Priority: Medium
battery voltage BATTERY_VOLTAGE_MAX?
Mains Detection (ADC Interrupt)
Minimum Charging Current
Turn Charger
Priority: Medium
Battery Charger Mode
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BATTERY CHARGER RESOURCE ALLOCATION FIGURE dsPIC® DEVICE RESOURCE ALLOCATION BATTERY CHARGER
VBAT Note Input
kA(2)
kB(2)
dsPIC33FJ16GS504
Note
mains input rectified body diodes IGBTs provide voltage battery charger. feedback gain circuits. Refer Appendix "Schematics Board Layout" details.
dsPIC device resources used battery charger summarized Table
TABLE
Signal Name IREF
dsPIC® DEVICE RESOURCE ALLOCATION BATTERY CHARGER
Description Charging current reference Charging current feedback Battery voltage feedback Flyback converter enable Type Signal output Analog Input Analog Input Digital Output dsPIC® Resource Used PWM4L (remapped Execution Rate/Frequency 6.25 6.25 Activated only when switches Battery Charger mode
Inverter Mode
mains voltage detected, battery charger disabled Offline switches Inverter mode. During Inverter mode, system running battery power produces clean sinusoidal voltage output that critical electronics continue operation without interruption. sinusoidal output waveform generated using sine lookup table data memory. This lookup table serves sinusoidal reference voltage inverter control loop.
When starting Inverter mode, push-pull converter ramped rated Link voltage using softstart routine. soft-start routine reduces stress system components also prevents voltage current surges from mains battery. During normal operation Inverter mode, pushpull converter full-bridge inverter controlled interrupt-based power conversion algorithms, control loops. control loops executed fast rate achieve best performance. Inverter mode power conversion algorithms most critical routines dsPIC device; therefore, these routines assigned highest user-priority level.
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state machine, which also interrupt-based, lower priority than control loops. result, execution state machine user interface code interrupted numerous times high-priority control loops. This operation possible because dsPIC device allows nesting interrupts. interrupt nesting feature enables control loops interrupt execution state machine. state machine execution relatively slower than control loops. dsPIC device allows seamless transition between power conversion routines state machine, with multiple interrupts differing priorities execution rates. When operating Inverter mode, system variables monitored state machine. soon mains voltage detected, switchover sequence engaged system state changed Battery Charger mode. system variable error, system state changed System Error.
PUSH-PULL CONVERTER INITIALIZATION
When system switches Inverter mode, previous modes operation must first disabled. Therefore, battery charger first disabled turning flyback converter also disabling output battery current reference. output relay engaged disconnect mains input from output, while inverter series resistor bypassed switching bypass relay. Then, push-pull converter control loop reinitialized control history purged. mains input wide operating voltage range; therefore, value link voltage unpredictable when mains failure occurs. result, before turning push-pull converter, most recently measured Link voltage used initial reference voltage push-pull converter. softstart routine enables Link voltage ramped controlled rate thus prevents unnecessary stress circuit components current spikes.
FIGURE
PUSH-PULL CONVERTER INITIALIZATION FLOWCHART
State Machine
Push-pull control loop (ADC Interrupt) Push-pull Converter Initialization Priority: Medium System Startup Priority: High Battery Charger Mode
Disable Battery Charger Flyback Converter Inverter control loop (ADC Interrupt) Turn signal battery current reference Switch output relay disconnect Mains from output
Priority: High
Bypass link charging resistor Battery Voltage Current Measurement (ADC Interrupt) Re-initialize push-pull control loop purge history
Priority: Medium
minimum duty cycle before turning outputs
Mains Detection (ADC Interrupt)
Enable outputs push-pull converter (PWM3H PWM3L)
Priority: Medium
Inverter Mode
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SOFT-START ROUTINE
soft-start routine called right after enabling push-pull converter. soft-start routine increments reference voltage push-pull converter software fixed steps until reference reaches rated Link voltage. this point, inverter enabled calling inverter re-initialization routine produce sinusoidal voltage output. ramp rate Link voltage fixed starting voltage soft-start routine variable, making soft-start duration also variable. variable duration soft-start routine cause uncertainty mains-to-inverter switchover time. ramp rate soft-start routine configured completed time required output relay turn This ensures that switchover time within design specification However, other situation must also considered where soft-start completed less time. this case, inverter output will turn before relay given enough time switch, thereby causing inverter output turned output midway through sine wave cycle. relay turned after completion soft-start, switchover timing would slow. dsPIC avoids both these problems initializing delay counter beginning softstart routine. soft-start routine ramping Link voltage, counter incremented reflect soft-start duration milliseconds. soft-start completed before minimum required time relay turn-on, code continues wait until minimum required switching time elapsed. Once required relay switching time elapses, full-bridge inverter enabled. This technique ensures that uninterrupted power available output times.
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FIGURE SOFT-START ROUTINE FLOWCHART
State Machine
Push-pull control loop (ADC Interrupt) Push-pull Converter Initialization Priority: Medium Start Push-Pull Soft-Start
Priority: High Initialize delay counter
Inverter control loop (ADC Interrupt)
soft-start flag allow higher peak currents during startup
Priority: High
Increment delay counter Increment push-pull reference Push-pull converter reference final setpoint?
Battery Voltage Current Measurement (ADC Interrupt)
Priority: Medium Increment delay counter Mains Detection (ADC Interrupt)
Does delay count represent duration greater than relay switching time? Clear soft-start flag
Priority: Medium
Inverter Mode
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FULL BRIDGE INVERTER INITIALIZATION
push-pull soft-start routine ensures that link voltage rated value output relay completed switching event. After soft-start routine concludes, full-bridge inverter must enabled produce sinusoidal voltage output. inverter control loop reinitialized purge control history. duty cycle then configured produce output sine wave lookup table pointer also reset start. this point, outputs enabled produce sinusoidal output voltage.
FIGURE
INVERTER INITIALIZATION FLOWCHART
State Machine
Push-pull control loop (ADC Interrupt) Inverter Initialization Priority: Medium
Priority: High
Inverter Mode
Inverter control loop (ADC Interrupt) Re-initialize inverter control loop purge control history
Priority: High duty cycle produce output
Battery Voltage Current Measurement (ADC Interrupt) Reset sine wave lookup table start
Priority: Medium
Enable outputs turn inverter (PWM1H, PWM1L, PWM2H PWM2L)
Mains Detection (ADC Interrupt) Inverter Mode Priority: Medium
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PUSH-PULL CONTROL LOOP
push-pull converter controlled with voltage mode control scheme. module dsPIC device configured Push-Pull mode with independent time-base. Link voltage measured converted digital value. This value subtracted from voltage reference software obtain voltage error. voltage error then into control algorithm that produces duty cycle value based voltage error, previous error, control history. output control algorithm also clamped minimum maximum duty cycle values hardware protection. voltage mode control algorithm must executed fast rate order achieve best transient response. Therefore, control algorithm executed interrupt service routine, which also assigned highest priority code. block diagram push-pull converter control scheme shown Figure
FIGURE
PUSH-PULL CONVERTER CONTROL SCHEME
1:16
VREF
Voltage Error
Control Output
Duty Cycle
VOUT
1001010111 Voltage Feedback
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INVERTER CONTROL LOOP
inverter output generated varying voltage reference using sinusoidal lookup table. measured output voltage subtracted from present reference value voltage error obtained. voltage error into voltage error compensation algorithm within interrupt service routine. output voltage error compensator produces current reference value. measured output current subtracted from current reference obtain current error. current error used input current error compensation algorithm produce command signal module. Offline UPS, 3-level control implemented full-bridge inverter. module dsPIC device with fixed duty cycle zero output voltage. Each full-bridge inverter operated complementary Center-Aligned mode with dead time. result control loop added nominal duty cycle full-bridge inverter subtracted from nominal duty cycle second leg. block diagram full-bridge inverter control system shown Figure
FIGURE
Sinusoidal Reference
FULL-BRIDGE INVERTER CONTROL SCHEME
Current Reference Current Error Current Feedback 1011010011 1001010111 Voltage Feedback Duty Cycle Output Filter
Voltage Error
Control Output
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PUSH-PULL CONVERTER HARDWARE SOFTWARE RESOURCE ALLOCATION FIGURE dsPIC® DEVICE RESOURCE ALLOCATION PUSH-PULL CONVERTER
Push-Pull Converter
VBAT
Driver
Driver
Analog Comparator
dsPIC33FJ16GS504
dsPIC resources used push-pull converter summarized Table
TABLE
Signal Name UDCM
dsPIC® DEVICE RESOURCE ALLOCATION PUSH-PULL CONVERTER
Description Push-Pull Drive Signal Push-Pull Drive Signal Push-Pull Primary Current Feedback Link Voltage Feedback Type Signal Output Output Analog Input Analog Input dsPIC® Resource Used PWM3L PWM3H Sample Rate/ Frequency
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FIGURE dsPIC DSC® RESOURCE ALLOCATION FULL-BRIDGE INVERTER
Full-Bridge Inverter
VOUT+
VOUT-
IGBT Driver
IGBT Driver
IGBT Driver
IGBT Driver
dsPIC33FJ16GS504
dsPIC device resources used fullbridge converter summarized Table
TABLE
Signal Name
dsPIC® DEVICE RESOURCE ALLOCATION FULL-BRIDGE CONVERTER
Description Inverter Drive Signal Inverter Drive Signal Inverter Drive Signal Inverter Drive Signal Inverter Output Current Feedback Inverter Output Voltage Feedback Mains Voltage Feedback Resistor Bypass Relay Drive Signal Type Signal Output Output Output Output Analog Input Analog Input Analog Input Digital Output dsPIC® Resource Used PWM1L PWM1H PWM2L PWM2H AN11 RC10 Sample Rate/ Frequency Activated only startup charge Link voltage above minimum value. Activated only when switches Inverter mode.
Output Relay Drive Signal
Digital Output
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Inverter-to-Mains Switchover Routine
When power failure occurs, Offline switches Inverter mode operates this mode until mains detected again. system should switch from mode other shortest possible duration order provide uninterrupted power load. Before switching Battery Charger mode, software must reliably ensure that mains voltage detected within specified levels. software must also ensure that mains waveform clean little distortion. mains detection routine divided into following steps: Mains High Voltage Detection: Inverter mode, software first checks presence high voltage mains. high voltage detected consecutively mains detection routine proceeds next step. Zero-Crossing Detection: After high voltage been detected, software keeps polling mains voltage zero-crossing detection. valid zero-crossing only detected previous voltage negative present voltage positive, difference between previous present measurement above minimum value. This ensures that spurious zero-crossings detected noise. Mains Data Collection: Once zero-crossing been detected, software enters mains data collection step. this step, every sample measured mains voltage stored array. Each sample collected data averaged over four sine wave cycles ensure accurate reference. This array later used mains reference detect mains failure. Mains Synchronization: After collecting mains voltage data, mains detection routine compares measured voltage with mains reference data. error within ±20V consecutively software concludes that mains present indicates state mains state machine. state machine then begins process switching from Inverter mode Battery Charger mode. switchover engaged zero-crossing both inverter mains. This provides smoothest transition from mode other occurs instantaneously. possible that inverter mains phase when mains available again. frequencies mains inverter nearly equal, zero crossings waveforms never align. Therefore, software first checks whether frequencies very close. there significant difference frequencies, waveforms will eventually align zero crossings, which when will engage switchover. signals operating nearly same frequency, inverter frequency modified slightly discarding some samples from lookup table. result, zero crossings signals forced align after sine wave cycles. This allows state machine switch from Inverter mode Battery Charger mode with almost zero latency. inverter-to-mains switchover sequence described graphically Figure also important note that alignment zero crossings must predicted using information relay switching time. relay switched milliseconds before actual zero-crossing that relay switching delay accounted for.
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FIGURE INVERTER-TO-MAINS SWITCHOVER SEQUENCE
Zero-crossing Detected Start Mains Data Collection Mains Data Collection Complete Zero-crossing Aligned High Voltage Detected
Mains
Inverter
Inverter turned Inverter Frequency Modified
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Mains-to-Inverter Switchover Routine
When mains present, software keeps comparing measured mains voltage with corresponding data mains reference array. quadrant information also saved variable. every sample, error between expected voltage actual voltage calculated. error detected larger than ±20V, count incremented. error detected outside limit consecutively about then Offline detects that mains failure occurred. system state changed Inverter mode relay switched immediately disconnect mains from output. push-pull converter then enabled soft-start routine executed. After softstart routine complete, mains voltage measured again. Using binary search algorithm, appropriate sample number from sine lookup table selected, which appropriate quadrant value closest mains voltage. inverter then enabled starting this sample number that there sudden change voltage output. mains-to-inverter switchover sequence described Figure
FIGURE
MAINS-TO-INVERTER SWITCHOVER SEQUENCE
Mains Failure detected Mains Failure Occurred Push-pull Soft-start Routine Completed Inverter turned last measured mains voltage
Output
Battery Charger Mode Mains Present)
Inverter Mode
Link Voltage
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System Error
goes into System Error state combination system variables detected fault state. state diagram Figure illustrates conditions under which system error detected. dsPIC device built-in fault current limit features that enable automatic shutdown power converters with software overhead. This feature critical power conversion applications useful protecting user, system hardware, downstream electronics. System Error mode designed handle faults after respective power stage been disabled. When system enters this mode, type fault displayed module. When enters System Error mode, system needs restarted again before function normally. instructions dsPIC device utilized efficiently execute calculation routines. library includes functions calculating sum-of-squares square-root. Both these operations available library, used implementing calculation offline reference design. calculation called idle loop since executed over mains cycle, therefore, requires relatively slow execution rate. results then scaled appropriately produce number volts amperes. order display result display, each decimal digit calculation result stored character variable. character variables then concatenated into string order display data module.
Auxiliary Tasks
non-critical functions Offline categorized auxiliary tasks. These tasks have relatively slow execution rate therefore assigned lowest execution priority Offline software. auxiliary tasks executed main loop code. These tasks performed only when other highpriority tasks like power conversion control loops state machine active. other words, auxiliary tasks performed during "idle" time power conversion routines state machine. result, main loop also referred "idle loop". auxiliary tasks numerously interrupted high-priority tasks like control loops state machine. Each auxiliary tasks described briefly following sections.
DISPLAY
control code dsPIC device implemented independent functions writing pixels, bytes, words, strings module. display routines called main loop. Offline Reference Design uses 4x20 character display module controlled dedicated (PIC18F2420). dsPIC device communicates with controller Serial Peripheral Interface (SPI). dsPIC device configured master device transmits commands controller. controller converts serial commands from dsPIC device into parallel data also manages timing controls module. Note: Operation controller beyond scope this reference design. Visit www.microchip.com/lcd design solutions.
OUTPUT VOLTAGE/CURRENT CALCULATION
Calculation routine provides output voltage current information display well output overcurrent output overvoltage/undervoltage protection. measured current voltage stored data memory array points each. When calculation routine called, respective array passed function, while output function true value parameter.
controller operates with supply dsPIC operates 3.3V supply. However direct connections between dsPIC controller made because digital-only pins dsPIC tolerant. Also digital outputs dsPIC operated open-drain configuration produce logic high controller using just pull-up resistor. resource allocation control summarized Table
TABLE
Signal Name
dsPIC® DEVICE RESOURCE ALLOCATION DISPLAY
Description Data Output Data Input Clock Output Type Signal Digital Output Digital Input Digital Output dsPIC® Resource Used RP22 RP19 RP21 Sample Rate/Frequency 156.25 when active 156.25 when active 156.25 when active
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Signal Name Description Slave Select Output Type Signal Digital Output dsPIC® Resource Used RP20 Sample Rate/Frequency Asserted only when data transmitted controller
COMMUNICATION
Offline also includes communication interface enable power management computer server connected UPS. communication performed separate controller (PIC18F2450). controller communicates with dsPIC device opto-isolated UART interface.
resource allocation communication interface summarized Table
TABLE
Signal Name
dsPIC® DEVICE RESOURCE ALLOCATION INTERFACE
Description UART Transmit UART Receive Type Signal Digital Output Digital Input dsPIC® Resource Used RP27 RP28 Sample Rate/Frequency 9600 9600
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Fault States Protection Schemes
There number fault sources that cause system turn outputs enter System Error mode. system fault trigger Offline enter System Error mode. These include following: Push-pull primary overcurrent Link undervoltage Link overvoltage Battery undervoltage Battery overvoltage Output overcurrent Overtemperature
Operation with Rectifier Loads
most important applications Offline provide uninterrupted power computers servers. Most computers servers implement switch-mode AC-DC power supply that implements Power Factor Correction (PFC). Such load usually contains front-end bridge rectifier therefore classified rectifier load. implemented, load appears highly capacitive load, resulting high peak currents power factor. block diagram connections such configuration shown Figure typical configuration such power supply contains boost converter shown Figure boost converter usually contains large output capacitor. seen from circuit diagram, impedance path exists from input output capacitor. result, output capacitor draws large inrush current when load first connected output.
system will enter System Error mode either single fault combination faults, depending operating modes. example, Link undervoltage condition will cause system enter System Error mode soft-start routine active. Similarly, transient loads cause pushpull primary current exceed limit short duration. Therefore, push-pull overcurrent fault will only generated overcurrent condition persists extended duration. faults that fast-acting destructive system user's load handled high-priority control loops. push-pull overcurrent fault example very high-speed signal that must detected quickly possible. result, this fault detected same time push-pull control loop. Other signals like battery voltage very highspeed signals therefore faults handled state machine. When fault condition happens, system enters System Error mode type fault displayed module.
FIGURE
TYPICAL RECTIFIER LOAD OFFLINE
Computer/Server Power Supply
Offline
Output
Input
Filter
Boost Converter
DC-DC Converter
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FIGURE BOOST CONVERTER
Load
implemented, current drawn load very discontinuous nature with high peaks, causing load appear highly capacitive, shown Figure
FIGURE
RECTIFIER LOAD INPUT CURRENT WAVEFORMS PFC)
Diode Diode Diode Diode Diode Diode Diode
Input Voltage
Output Voltage
Input Current
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presence large capacitor output boost converter, Offline needs implement special algorithm handle load steps startup conditions rectifier loads. current draw during rectifier load startup times maximum rated current. option support these high current surges design hardware with sufficient design margin. However, this approach usually cost effective also cause drop performance efficiency. dsPIC provides number flexible features overcome this problem. Current-Limit feature used limit current cycle-by-cycle basis. This feature, along with software help charge output capacitor controlled manner that inrush current limited. Offline Reference Design, external interrupt generated when overcurrent condition occurs. This causes module automatically shut down. Inside Interrupt Service Routine, configured very small duty cycle then re-enabled. duty cycle small, current drawn during switching cycle automatically limited. duty cycle incremented small steps charge output capacitor controlled manner. While current-limit fault handling routine being executed, inverter control loop overridden. inverter control loop resumes operation when sine voltage reference inverter becomes equal actual voltage inverter output. first current limit fault caused short circuit condition inverter output, current limit fault will triggered immediately second time. This will cause system shut down with overcurrent error. error state displayed display module reset only when system turned back
Peak Current Limiting Function
power factor rectifier load low, will result high crest factor inverter current. Offline Reference Design rated maximum crest factor 3:1. crest factor load exceeds this value, action taken current within maximum peak current rating. However, high crest factor warning displayed display module. peak current required load exceeds 15A, current limiting function overrides inverter control loop. This function limits maximum current output clamping duty cycle maximum value.
Offset Elimination
side-effect operating with high crest factor that current drawn become asymmetric. This caused presence small offset inverter output voltage. offset occurs tolerance limits feedback components. typical analog implementation requires trimming resistors eliminate offset. This solution requires trimming each system during manufacturing, therefore becomes expensive time consuming. also need periodic adjustment servicing schedule account effects long term degradation components. dsPIC helps overcome this problem with active algorithm eliminate offset. Offline Reference Design implements offset elimination routine comparing positive negative peak measured output voltage. imbalance detected, correction factor applied output voltage cancel offset. peaks determined averaging maximum minimum recorded voltages over number sine wave cycles. Doing helps ignore effects load steps output.
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HARDWARE DESIGN
Push-Pull Boost Converter
DESIGN SPECIFICATIONS
push-pull boost converter needs convert wide range battery link input voltage stabilized high-voltage DC-Link. design specifications used Offline Reference Design are: Input voltage range: 30-45 Output voltage: Continuous power: Peak power seconds: Switching frequency:
TOPOLOGIES CONSIDERED REASONS CURRENT CHOICES
Figure Figure possible push-pull boost circuits shown. combination push-pull inverter (Figure 39(C)) full-bridge rectifier (Figure 40(B)) chosen, which provides best price performance ratio. inverter only lowside drive circuitry required simple signals (see Figure drive inverter.
FIGURE
PRIMARY DRIVE CIRCUITS
Full-Bridge Inverter
Half-Bridge Inverter
Push-Pull Inverter
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FIGURE RECTIFIER CIRCUITS
Half-Bridge Rectifier
Full-Bridge Rectifier
FIGURE
CONTROL SIGNALS PUSH-PULL INVERTER
output voltage calculated Equation where transformer windings ratio, duty cycle signal. duty cycle must limited given boundary. real application, duty cycle must limited 0.42. This done switching behavior MOSFETs transformer. allowed oscillation losses system, calculation using Equation exact. When load applied push-pull boost stage, controller switch into Burst mode, when heavy load applied, duty cycle must increased compensate various losses.
EQUATION
secondary, full-bridge rectifier chosen following reasons: Reducing leakage inductance using only secondary winding transformer Reducing cost transformer Rectifier diodes rated lower reverse breakdown voltage, such diodes have better forward switching characteristics. Synchronous rectification required high-voltage current operation.
where: duty cycle transistors N2/N1 secondary-to-primary turns ratio transformer
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DESIGN POWER-TRAIN COMPONENTS
push-pull transformer been designed using ferrite magnetic core. transformer design based using area product (WaAc) approach designed meet following conditions: Minimum input voltage: Vimin Maximum link voltage: 380V Maximum output power: Pomax 2000W Primary current: IPrms 30.5A Maximum duty cycle: Dmax 0.42 Switching frequency: from FERROXCUBE selected. From core loss, maximum flux density calculated, shown Equation factors used this equation provided Table
EQUATION
Core loss density normally selected around cm3. calculated maximum flux density must limited less than half saturation. This level chosen because transformer core will develop excessive temperature rise this frequency when flux density close saturation. Maximum flux density calculated, shown Equation
manufacturer's data sheet used help select appropriate material desired application. given range materials, frequency, core loss, maximum flux density material should considered. From research data, 3C90 material
TABLE
Material
FACTORS APPLIED EQUATION (CORE LOSS EQUATION)
Frequency 0.074 0.036 0.014 0.158 0.0434 7.36e-7 0.790 0.0717 0.0573 0.0126 1.43 1.64 1.84 1.36 1.63 3.47 1.06 1.72 1.66 1.88 2.85 2.68 2.28 2.86 2.62 2.54 2.85 2.66 2.68 2.29
35G, N87, 3C90
45G, N72, 3C85
25G, N41, 3C81
EQUATION
2.68 1339G 1.64 0.036 100000 1000 1000 1000 1000
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selecting right size core, area product core must calculated Equation This equation derived from flux linkage equation represents power handling ability core. Therefore, each core number that product window area, core cross-sectional area,
FIGURE
HYSTERESIS LOOP MAGNETIC CORE
BSAT
EQUATION
omax Equation equal 2Bmax bidirectional core excitation seen Figure Current density winding estimated 500A/cm2, maximum output power Pomax 2000W. Therefore, calculated area product shown Equation
BMAX
BMAX
EQUATION
2000 5.9cm 0.254 2678 100000
BSAT
selected core must have area product larger than calculated. ETD54 shape size core selected with WaAc 12.6 cm2. larger size selected primary secondary windings, which winding area that core. primary turns calculated Equation Given result then rounded down integer value. this case rounded turns one-half primary.
EQUATION
imin Dmax 0.42 100000 2678
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secondary turns calculated Equation result rounded value secondary turns. much higher short winding. Primary current IPrms 30.5A. Secondary current calculated Isrms IPrms 2.03A.
EQUATION
0.42 60.3 imin cross section primary secondary windings calculated Equation Different current densities used 8A/mm2 5A/mm2) windings into transformer bobbin because length one-half primary very short compared secondary. that case, allowed higher current density primary temperature winding will
EQUATION
Prms 3.81mm Srms AcuS 0.41mm Because high switching frequency, kHz, litz wire must selected reduce winding losses (losses skin proximity effect). Litz wire must also designed that frequency. Figure shows transformer winding diagram construction diagram.
FIGURE
TRANSFORMER ELECTRICAL MECHANICAL CONSTRUCTION
Bobbin CORE Insulation Shield
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PUSH-PULL MOSFETS
When choosing right MOSFETs following must considered: Maximum Breakdown Voltage Continuous Current Peak Current Package Thermal Performance
Peak Current
peak current must calculated maximum power form current waveform must also taken into account. When assume that current waveform will have sawtooth waveform with given duty cycle (d), calculate resulting peak current using Equation duty cycle calculated using Equation
Maximum Breakdown Voltage
chosen configuration, MOSFET must able hold more than twice battery voltage, expressed Equation this calculation, safety factor overrating chosen. Therefore, selected devices need have drain-to-source breakdown voltage higher than 117V.
EQUATION
Pmax
EQUATION
EQUATION
VBRDSS 2VBAT 117V
Continuous Current
calculate current rating devices, peak average currents have estimated. peak average currents estimated from power ratings input voltage. average current calculated using Equation where continuous power UBAT battery voltage.
When transformer with windings ratio peak current that Equation
EQUATION
2000W 160.3 0.416
EQUATION
highest current will flow lowest battery voltage continuous current 1000W 33.34A. leg, continuous drain current half this: 16.67A.
Therefore, have design MOSFETs continuous drain current 16.67A peak drain current 160.3A. Because waveform shape will exact sawtooth, these calculations only estimate. safe side, these numbers increased 30%.
Package Thermal Performance
design thermal performance, current value must calculated. waveform shape peak current known, calculated using Equation
EQUATION
current calculated shown Equation
EQUATION
80.15
.416 42.13
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leg, current half this: IDRMS 21.07A This most critical design consideration; therefore, overrating should done IDRMS 21.07A 31.5A, current leading traces transformer should also rated this current. conductive losses MOSFETS calculated using Equation MOSFETs selected. reference design, TO-220 package used MOSFETs. Typical junction-to-heat sink thermal resistance these devices 2.5°C/W when using silicone insulation. will allow continuous junction temperature 110°C heat sink temperature 60°C. From this power dissipation, calculate needed thermal resistance, which provides number parallel MOSFETs use. number necessary devices calculated 2.7. According calculation shown Equation three parallel FDP2532 devices from Fairchild Semiconductor were selected.
EQUATION
Drms RDSon
switching frequency with push-pull configuration also switching, losses have taken into account. current waveform near sawtooth, turn-on losses neglected. Turn-off losses depend peak current leakage inductance. limit voltage spikes turn-off voltage clamp circuit used. This circuit enables MOSFETs operate without snubbers. Snubbers only used suppress high frequency oscillation, dissipate energy stored leakage inductance transformer. Therefore, energy dissipated MOSFETs. Equation used estimate power dissipation turn-off.
EQUATION
0.91C Ptot
EQUATION
Poff
Equation energy stored leakage inductance turn-off calculated using Equation
EQUATION
typical transformer this range should have more than leakage inductance. Therefore, turn power would that Equation
EQUATION
Poff 100e3
1.6e3
Total dissipation MOSFETS then Ptot Poff estimated leg.
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FULL-WAVE RECTIFIER FIGURE RECTIFIERS WITH CURRENT FLOW
Conduct
Conduct
When selecting diodes, following must considered: Diode Breakdown Voltage Average Forward Current Peak Forward Current Switching Characteristics Package Thermal Performance
Average Forward Current
Average forward current easily calculated using Equation from desired link voltage continuous output power.
EQUATION
Diode Breakdown Voltage
transformer secondary voltage calculated VBAT maximum secondary voltage highest battery voltage 720V Because transformer leakage inductance, diode internal inductance, link inductor inductance, voltage spikes appear diodes when switching. this, calculated breakdown voltage increased should more than 936V.
1000
Peak Forward Current
Peak current calculated using transformer current ratio peak MOSFET current previously calculated Equation
EQUATION
160.3 0.625
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Switching Characteristics
Diode switching characteristics determined forward recovery time reverse recovery time.
FIGURE
DIODE SWITCHING CHARACTERISTICS i[A] u[V]
PDon
PDoff
t[s]
Diode switching Equation
loss
estimated
using
Total power loss estimated adding conduction losses switching losses, shown Equation
EQUATION
EQUATION
PswD
Package Thermal Performance
diodes, isolated TO-220-2 package used. Continuous working junction temperature should exceed 130°C heat sink temperature 60°C. Typical thermal junction-to-heat sink resistance junction-isolated TO-220-2 package 3.5°C/W. Therefore, maximum allowed power dissipation part PMAX 20W. STTH1210DI from STMicroelectronics meets voltage current requirements. Power loss calculation done looking diode data sheet.
Ptot PswD
estimation shows that power losses within criteria.
Output Inductor
This inductor optional required. depends transformer construction control DC-link voltage, inductor value that must used. This section describes design output inductor. design output inductor uses area product approach with following conditions: Inductance: Peak current: Operating flux density: Current density: 500A/cm2 Window utilization:
First, energy handling capability must calculated Equation
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EQUATION EQUATION
0.0043Ws
Bnew
308mT
Then, select appropriate size ferrite core, area product calculation must done, shown Equation
3C81 material saturation point (100oC). criteria fulfilled, different material, gap, number turns, even bigger core must selected. cross-section wire calculated Equation where current through inductor calculated from primary current push-pull transformer turns ratio. This current twice large primary because half switching period, first primary winding conducting other half, second primary winding.
EQUATION
1.43cm
selected core P36/22 core from FERROXCUBE small size shape, which produces less interference into surrounding components. area product this core 1.46 calculated from data manufacturer's data sheet. number turns required desired inductance coil calculated Equation Core cross section obtained from manufacturer's data sheet.
EQUATION
Prms
0.82mm2
EQUATION
calculated value minimum cross-section wire (100 litz wire must used). Next, fill factor must calculated Equation This provides estimation whether winding fits into bobbin. fill factor must less. bobbin winding area 72.4 mm2, found core data sheet.
12.6
calculated number turns then rounded nearest integer value, which desired inductance, 3C81 material with selected control flux density. distributed into magnetic path core, effective permeability material changes inductance factor From value number turns, inductance calculated Equation value obtained from material data sheet 0.97 gap.
EQUATION
0.15
Output Capacitors
When choosing DC-link capacitors, following must considered: Voltage Rating Ripple Current
EQUATION
operating flux density verified Equation must lower than saturation point selected material.
Voltage Rating
voltage rating defined Link voltage: 380V. Therefore, capacitors must above this rating.
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Ripple Current
When link voltage controller working expected, frequency ripple current caused inverter negligible. Therefore, capacitors need only compensate reactive load current, which depends device specifications: 1300VA 1000W.
EQUATION
EQUATION
830.7Var
EQUATION
SNUBBERS
830.7
Damping system very because primary winding resistance (RS) series resistance battery link capacitors (RC), which both range milliohms. reduce this high frequency ringing, series snubbers were added across primary winding. capacitance should three times capacitance MOSFETs, series resistor value should chosen that grants damping power dissipation within resistor rating. maintain high efficiency system allow less than rated power dissipated primary snubbers. final values snubber evaluated experimenting power rating resistors design snubbers rectifier diodes, capacitance rectifier diode must known. simplified high frequency circuit shown Figure
Snubbers used dampen high frequency oscillation reduce ringing losses diodes. Snubbers primary side placed across primary windings used handle voltage spikes turnoff MOSFETs. They only reduce ringing transformer in-rush current. design snubber primary side, capacitance MOSFETs leakage inductance transformer must known. Both parameters measured; however, MOSFET capacitance voltage dependent only estimate used. case, capacitance three parallel MOSFETs approximately leakage inductance transformer estimated simplified high frequency circuit shown Figure
FIGURE
HIGH-FREQUENCY CIRCUIT
FIGURE
HIGH-FREQUENCY CIRCUIT
Here, capacitor should range from five times capacitance diode. diode capacitance found diode data sheet. selected diodes approximately Therefore, good starting capacitance value snubber Here will also limit maximum waste power rated converter power keep efficiency converter high possible. Thus, resistor ratings will also resistor value should selected that main switching voltage signal will produce possible dissipation resistor. dissipation dependent frequency characteristics, selecting lower resistance lower capacitance will shift characteristic frequency circuit higher, which result switching voltage producing less dissipation snubbers. However, damping snubbers will also decrease. good starting value resistor
resonant Equation
frequency
calculated
using
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Calculating required snubber circuit very complex does give expected results. Therefore, parameters have evaluated experimenting. When designing snubbers following must considered: Overall system efficiency Signal quality Device power ratings Device voltage ratings ensure resistance state gates driven with signals. drive circuit shown Figure which consists driver shown slope control elements, equalization resistors turn-off voltage clamp circuit elements optional. used ensure MOSFETs turn themselves. used compensate Miller capacitance control. Resistors used equalize gate threshold voltage MOSFETs ensure parallel turn-on. combination with turn-on slope also controlled. addition, turn-off slope controlled until drain-to-source voltage (VDS) reaches voltage clamp circuit threshold. When voltage clamp circuit becomes active, stays constant turn-off slope reduced. This enables part energy stored leakage inductance transferred secondary side other part dissipated controlled fashion MOSFETs. Also, overall system oscillation reduced lower current slopes. However, must considered that turn time MOSFETs will increase that maximum duty cycle must reduced. Driver continuous supply current calculated using Equation Where number parallel MOSFETs.
Design Drive Circuitry
drive MOSFETs, driver must used that amplifies signal from dsPIC device drives gates MOSFETs. gate MOSFET behaves like capacitor. MOSFET drain-to-source depends gate source voltage, VGS. higher gate-to-source voltage, lower drainto-source resistance MOSFET. selected MOSFETs: ±20V VGS(TH) 2-4V CG(TOT) 10.7
FIGURE
MOSFET DRIVE CIRCUIT
Zener
EQUATION
(tot VDRV 10.7 96.3mA
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Peak current estimate calculated using Equation
Thermal Design
heat produced MOSFETs diodes must transferred ambient using heat sinks. Total power loss estimation which were performed earlier are: MOSFETs, PMOS 110W diodes, PDIODE 40W. Forced cooling used dissipate heat
EQUATION
VDRV
Driver power dissipation calculation shown "MCP14E3/MCP14E4/MCPE5 4.0A Dual High-Speed Power MOSFET Drivers With Enable" (DS22062) data sheet. total power dissipation calculated approximately Ptot
Full-Bridge Inverter
INVERTER DESIGN SPECIFICATIONS
inverter used generate output voltage. specifications are: Input voltage Output voltage: VACrms Continuous power: Continuous output current: Arms Peak power seconds: 1300 Maximum output current: Arms Switching frequency: Short circuit-proof
Design Voltage Current Feedback Circuitry
push-pull stage, battery link, link voltage, measurements needed. Both measurements done differential with MCP6022 rail-to-rail operational amplifiers. When taking high voltage differential measurements, input resistance must high voltage power rating resistors must exceeded. Because this, 1206 resistors used input dividers reference design. output signal differential amplifiers increase SNR. Then, resistor divider used near dsPIC interface 3.3V, 10-bit converter. addition, capacitor placed near dsPIC enable fast charge capacitor. measurement, tolerance resistors used. This especially important differential amplifiers guarantee same resistance both arms reduce common mode noise rejection. MOSFET drain current heat sink temperature also measured. current measurement based voltage drop measurement drain-tosource resistance, RDSON. This type measurement temperature dependent semiconductor temperature sensor placed which nearly same temperature dependency MOSFET, RDSON. current feedback signal used prevent transformer from saturating.
INVERTER POWER-TRAIN DESIGN IGBT Selection
high switching frequency, IGBTs with switching losses must selected. Their voltage rating should 600V with current rating more continuous. STGP14NC60KD from STMicroelectronics chosen fulfils selected criteria. Loss estimation done using information data sheet estimated 17W. estimated junction-to-heat sink resistance using SilPad 3°C/W. According these estimates, junction temperature will raise 50°C above heat sink temperature. IGBT inverter also acts full-wave rectifier when charging battery from power grid.
Layout Considerations
push-pull stage, special care should taken with traces leading primary current. High frequency currents high current peak values produce noise even losses PCB. Therefore, traces should short possible they should contain sharp edges. good idea connect primary windings with transformer litz wire that used winding transformer (fly leads). Care should taken couple power signal parts with ground planes.
Output Common-mode Choke
common mode inductor windings same core. called common mode because blocks common mode interference switching noise produced inverter output. schematic inductor shown Figure windings indicates start winding. When load connected output, flux core must summed; otherwise, inductor connected incorrectly.
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FIGURE COMMON MODE INDUCTOR SCHEMATIC EQUATION
39.9
Input
Output
calculated number turns number both windings. number rounded value that both winding have equal number turns, which desired inductance, value calculated Equation
EQUATION
Design output common-mode choke same design that inductor, with following conditions: Inductance: Peak current: Operating flux density: Current density: 500A/cm2 Window utilization: Output power: 1000W must
156nH
Now, from core manufacturer's data sheet correct selected. Epcos material, length calculated with Equation
EQUATION
First, energy handling capability calculated, shown Equation
EQUATION
3.3mm
chosen from data sheet value must calculated Equation
0.036Ws
After that, select appropriate size core, area product calculation must done, shown Equation
EQUATION
148nH
inductance value shown Equation
EQUATION
10.3cm
selected core Epcos ETD54 ferrite core. area product that core 11.5 cm4, calculated from dimension data manufacturer's data sheet. number turns required desired inductance coil calculated Equation core cross-section, mm2, obtained from manufacturer's data sheet.
EQUATION
operating flux density verified Equation must lower than saturation point selected material.
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EQUATION Output Relays
Bnew
360mT
material saturation point (100oC). cross section wire calculated Equation where current through inductor calculated from output power value output voltage.
EQUATION
230V 0.88mm
calculated value minimum cross-section wire (100 litz wire must used). Next, fill factor calculated Equation This will give estimate windings will into bobbin. fill factor must less. bobbin winding area 315.6 mm2. This information found core data sheet.
relays used system. Relay used control charging link capacitors from power grid. During operation this relay always Relay used switchover when power grid fails. This relay must have fast switchover time additional components used reduce switchover time. R||C combination used allow high current turn-on, then reduce current during state allow faster turn-off. Resistor used deplete energy stored relay coil faster turn-off. Transistor Q11's switching speed increased using R-C||R combination, which allows higher base current turn-on negative voltage base current turn-off.
DESIGN GATE DRIVE CIRCUITRY
half-bridge driver with fault- short-circuit protection must used fulfill design specification. selected IGBT withstand short circuit driver detects short-circuit, will perform soft turn-off IGBTs. addition, bootstrap with 600V floating channel needed drive high-side IGBTs. able meet requirements, turn-on turn-off slopes should tunable with gate resistors. IR2214 from International Rectifier meets these requirements. Looking data sheet IGBTs allowed gate voltage VGMAX ±20V gate threshold voltage VG(TH) 4.56.5V. driver supplied ensure IGBT turn-on. ensure that IGBT does turn internal IGBT Miller capacitance when rises with high slope, gate collector capacitors used.
EQUATION
0.11
Output Capacitor Selection
Inverter switching transistors produce sinusoidal pulse width modulated voltage waveform that fundamental frequency low-pass filter comprises output inductor output capacitor pass only low-frequency component sinusoidal pulse width modulated voltage waveform, order produce low-frequency sinusoidal output voltage. value output capacitor must large enough pass fundamental frequency enough that should need high reactive current. cutoff frequency ~100 value output capacitor selected output capacitor should able take high inductor ripple current well suppress switching noise. B32924C3475M series film capacitor from Epcos fulfils selected criteria.
DESIGN VOLTAGE CURRENT FEEDBACK CIRCUITRY
voltage feedback, differential amplifiers used, which built with MCP6022 operational amplifier. measure power grid output voltage, bipolar measurements needed. enable differential amplifiers measure bipolar signal voltage, offset Voff 2.5V used positive reference point. Therefore, operational amplifier gives 2.5V output when differential measured voltage zero. When differential measured voltage negative, output goes conversely, output voltage goes when measured differential voltage positive.
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Because high differential input voltage, series 1206 resistors were used stay within voltage power rating devices. resistors used were tolerance guarantee exact measurement reduce common mode noise rejection. current measurement, Hall effect-based sensor from used. sensor bipolar signal output 0.5V. zero current, output 2.5V. signals, resistor divider added near dsPIC interface with 3.3V 10-bit converter. addition, capacitor added near dsPIC fast-charge capacitor. clamping elements designed using design tools from manufacturer TOP250Y.
Flyback Transformer
flyback transformer designed desired output power output current ripple, enable current source operation. flyback converter, transformer with needed. transformer designed following conditions: Minimum link voltage: Vimin 130.6 Maximum link voltage: Vimax Nominal link voltage: Vinom 247.4 Nominal duty cycle: 0.24 Output current: Io1max 2.5A Nominal output voltage: Secondary current ripple: Is[%] Switching frequency:
LAYOUT CONSIDERATIONS
Traces leading output current should held short possible. Special care should taken because high voltage. Around IGBT driver logical level gate drive components should separated, care should taken couple parts with ground planes.
primary secondary turns ratio calculated with Equation
THERMAL DESIGN
IGBTs must placed heat sink dissipate produced heat. Total power dissipation estimated PIGBT 68W. devices must mounted heat sink using thermal conductive electric insulating material.
EQUATION
Vinom VDSon
Battery Charger Design
DESIGN SPECIFICATIONS BATTERY CHARGER SPECIFICATIONS
battery charger used charge batteries from power grid. Three series lead acid batteries were used system. charger design specifications are: Input voltage: 95-260 Output voltage: 30-45V Output current: 0-2.5A Current control Voltage limit
limit current ripple, inductance primary secondary windings must calculated with Equation
EQUATION
Now, primary current calculated with Equation where transformer efficiency estimated 90%, secondary current with Equation
DESIGN POWER-TRAIN COMPONENTS
realize flyback converter primary drive stage, integrated solution TOP250Y from Power Integrations selected. Maximum output power calculated UBmax IBmax 112.5W flyback works with switching frequency kHz. Therefore, fast rectifier primary clamp diode must used. transformer ratio Based this ratio maximum input voltage, rectifier reverse voltage rating should higher than result Equation where VF(IGBTD) voltage drop across IGBT anti-parallel diode, which used power grid voltage rectification.
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EQUATION
Speek
Speek
Speek
EQUATION
0.55
Ppeek
selected core needs have higher area product than what been calculated. From magnetics side, ETD34 above will sufficient; however, there needs enough space windings. this iterations different cores, number turns from this window utilization fill factor calculated. window utilization higher than fill factor higher than 0.4, windings will fit. transformer construction winding diagram mechanical diagram shown Figure
Ppeek
Prms Ppeek
Now, required wires primary secondary selected. will design flyback transformer current density A/mm2. Therefore, required copper area primary secondary calculated with Equation (litz wire must used).
EQUATION
ACuP ACuS
Prms 0.375mm Srms 0.8mm
winding factor selected transformer material core. maximum core flux density select core, area product calculated with Equation
EQUATION
0.65cm
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FIGURE TRANSFORMER ELECTRICAL MECHANICAL CONSTRUCTION
Primary Bobbin Primary Secondary Primary CORE Insulation Shield Secondary Primary
windings, litz wire used grant copper losses high frequency. switching frequency kHz, litz wire made AWG38 wires used eliminate skin proximity effect. required number parallel wires calculated with Equation
EQUATION
16.7
EQUATION
ACuP 47.7 ACuw ACuP 101.8 ACuw
EQUATION
2.32 1.875
both, have select standard litz wires. primary, 45xAWG38 selected secondary, 105xAWG38 selected. diameter selected wires with silk isolation used ETD39 core with gap, required number turns calculated from required primary inductance, turns ratio, core data. Primary turns calculated with Equation
window utilization shown Equation fill factor Equation
EQUATION
EQUATION
58.1
EQUATION
Ppeek
30.5
ACuP ACuS 0.25
According this windings selected core. required calculated from core data sheet. calculate required value core calculated. value dependent. From knowing primary inductance number winding turns, required value calculated with Equation
Now, window utilization fill factor calculated selected core wires. bobbin window 25x7 From this calculated many turns primary secondary (Equation number required layers (Equation 61).
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EQUATION
203.3nH
VOLTAGE, CURRENT TEMPERATURE SENSE CIRCUITRY
battery charger works current source delivering requested charge current battery, independent battery voltage. current measurement control, resistor high-side current shunt monitor (INA168 from Texas Instruments) were used. current control, discrete analog controller built that controls duty cycle TOP250Y. addition, measured current through differential amplifier stage dsPIC device. Parallel current feedback loop, voltage feedback loop used limit output voltage case battery connected. addition, header placed interface with temperature sensor monitor battery temperature allow battery management software know state batteries.
Now, from core manufacturer data sheet, correct selected. used EPCOS ETD39 core, correct calculated with Equation
EQUATION
0.95mm
nearest standard values calculated value close select need change windings. selected, number winding turns must corrected.
LAYOUT CONSIDERATIONS
Precaution must taken high voltage signals. Also primary clamp components should placed near possible transformer TOP250Y reduce stress switching components. Care should also taken couple power, control, measurement parts with ground planes.
Battery Selection
battery selection will depend voltage required backup time Offline system. Offline Reference Design been designed input voltage, being able produce hour backup time with battery.
THERMAL DESIGN
switch rectifier diode must mounted heat sink. Assuming efficiency battery charger 70%, nearly loss will dissipated. Those losses consist clamp losses, transformer losses, primary switch (TOP250Y), rectifier losses. Therefore, estimate that near losses need dissipated heat sink. Both elements TOP250Y rectifier diode must mounted heat sink using thermal conductive electrical insulating material.
EQUATION
rect
Vbat IGBTD 240.4V
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Design Auxiliary Power Supply
DESIGN SPECIFICATIONS
auxiliary power supply provides power, which taken from battery link, on-board electronics. design specifications are: Input voltage: 30V-45V Output: 3.3V,
CONCLUSION
Microchip dsPIC device provides necessary power peripherals used power conversion applications. It's highly flexible Intelligent Power Peripheral (IPP), ADC, Comparator, modules simplify hardware schematic reduces number components design high-performance system. built-in engine help optimizing control loop design, being able produce clean sine wave output (THD less than even with rectifier load crest factor 3:1. With help optimized instruction sets, like MAC, there enough time left perform auxiliary tasks, fault protection, housekeeping, communication with external world. dsPIC33F enables power conversion design with advance features within target price.
CHOICE COMPONENTS
Because wide range input voltage power losses, buck converter used generate from battery voltage. 3.3V linear regulators used because simplicity price. voltage regulators connected series buck converter needs deliver current. buck converter, LM5575 from National Semiconductor used with switching frequency kHz. Components were selected according LM5575 data sheet. linear voltage regulators, power dissipation must calculated select right package layout. regulator, maximum power dissipation calculated (VIN VOUT) IOUT 3.15 3.3V (VIN VOUT) IOUT regulator, (KE7805ER) TO-263 package with mount heat sink selected, 3.3V regulator, (TC1262) SOT223 package selected. analog circuits, additional chip inductors capacitors were added separate digital analog supply voltages. auxiliary power supply will start when link voltage present when button pressed.
REFERENCES
"MCP14E3/MCP14E4/MCPE5 4.0A Dual HighSpeed Power MOSFET Drivers With Enable" (DS22062), Microchip Technology Inc. "TC1262 500mA Fixed Output CMOS LDO" (DS21372), Microchip Technology Inc. "Power Electronics Converter, Applications Design" N.Mohan, T.M. Undeland, W.P. Robbins "Control Topology Options Single-Phase Inverter" Ryan, W.E. Brumsickle, R.D. Lorenz, IEEE transaction industry application, Vol. March/April 1997. Current Mode Control Technique with Instantaneous Inductor Current Feedback Inverter" H.Wu, D.Lin, Zhang, Yao, J.Zhang, IEEE transaction, 1999. High Performance Sine Wave Inverter Controller with Capacitor Current Feedback BackEMF coupling" Ryan R.D. Lorenz, IEEE transaction, 1995.
LAYOUT CONSIDERATIONS
buck converter, very high frequency current, care should taken when designing output traces. inductor, Schottky diode, low-ESR output capacitors should close possible Also input capacitors should placed close block noise produced buck converter. linear regulators, adequate copper area must provided keep devices cool.
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NOTES:
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APPENDIX SOURCE CODE
Software License Agreement
software supplied herewith Microchip Technology Incorporated (the "Company") intended supplied you, Company's customer, solely exclusively with products manufactured Company. software owned Company and/or supplier, protected under applicable copyright laws. rights reserved. violation foregoing restrictions subject user criminal sanctions under applicable laws, well civil liability breach terms conditions this license. THIS SOFTWARE PROVIDED CONDITION. WARRANTIES, WHETHER EXPRESS, IMPLIED STATUTORY, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE APPLY THIS SOFTWARE. COMPANY SHALL NOT, CIRCUMSTANCES, LIABLE SPECIAL, INCIDENTAL CONSEQUENTIAL DAMAGES, REASON WHATSOEVER.
software covered this application note available single WinZip archive file. This archive downloaded from Microchip corporate site www.microchip.com
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APPENDIX CONTROL SYSTEM DESIGN
circuit. system implementation based integrators saturations. input typically voltage given modulation block (conversion duty ratio actual excitation voltage). Depending topology, power system block will change. Parasitic components such capacitor inductor included system here. addition, loading system will accounted here.
Offline Reference Design implements full digital control push-pull converter full-bridge inverter. MATLAB® used design compensators based hardware generate optimal coefficients used software.
MATLAB SIMULINK
simulation files contain models various subsystems. Some subsystems presented nested blocks simplify main diagram. Simulink® provides mathematical blocks time domain simulations. There typically models each file. Analog implementation Digital implementation Each file analog implementation typically consists following sections: Reference Block Feedback System Block Power System Block Control System Block Modulation Inverse Block Modulation Block Load System Block Special Blocks
CONTROL SYSTEM BLOCK
This block generates duty ratio that drives power section block. feedback signals from feedback block input output number between which represents duty cycle ratio. This block consist various cascaded loops based control scheme (voltage mode current mode control). digital implementation integrators differentiators replaced their digital equivalents.
MODULATION INVERSE BLOCK
This block part control system block converts output loops from voltage current quantities duty ratio quantities between Different topologies have different implementations. Typically, involves division with voltage quantity (e.g., input voltage buck converter output voltage boost converter). just inverse operation modulation performed physical system converting duty ratio into voltage. These models typically have division with voltage quantity (divisor) with little variation. Sometimes software these routines implemented, actual system, quantity assumed constant gains prescaled appropriately.
Simulink blocks will vary based converter topology control scheme implemented (i.e., current mode, voltage mode). following sections describe each block used within models.
REFERENCE BLOCK
This system provides input control system. Typically, only constant DC-DC converters sine wave generator UPS-type models. control system required track reference waveform. This block labeled such actual models.
MODULATION BLOCK
This block represents average model switching system. This block converts duty applied physical system voltage quantity. input duty cycle ratio /parameter that gets converted voltage quantity. usually takes system input voltage duty cycle input generates output voltage.
FEEDBACK SYSTEM BLOCK
Various signals typically measured system. These include voltages currents performing control operations. digital implementation, additional blocks needed account quantization presence zero order holds sampling signal constant frequency.
LOAD SYSTEM BLOCK
This block used generate different types load current. example, step load with offset created, which useful step loading. Sinusoidal loads UPS-type systems with variable phase (inductive, resistive, etc.), amplitude, frequency also used depending choice test conditions.
SPECIAL BLOCKS
Second order effects like saturation inductor dead-time modeled systems where these become important like UPS. These indicated saturation dead-time blocks.
POWER SYSTEM BLOCK
This actual physical system. This system represents energy states what actually gives output controlled. Typically, will consist
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MATLAB File
file used generate coefficients that used MATLAB model (.mdl). also generates scaled values used software. generated values fractional format. software they must represented Q15(x), where fractional value. following parameters typically used: input voltage (equivalent inductor value) (equivalent capacitor value) (capacitor ESR) (lumped series resistance includes tracks switch cable resistance, etc.) Depending implementation, input voltage assumed constant lumped together with some gains. Bode plots generated file graphical representation. following typical plots: Loop gain plot this used determine phase gain margin Closed loop plot used determine closed loop response bandwidth system Disturbance rejection plot Io(s) Vo(s) used determine stiffness system expected amount voltage ripple when load applied function frequency
Based topology used, these parameters vary from actual values. example, three converters parallel, then simulation performed single converter (instead (3x) capacitor value, only single capacitor modeled inductor value will remain same). input voltage vary especially when transformers involved. Typically, quantities then referenced primary secondary based convenience. either case, input voltage will vary.
Push-Pull Compensator
push-pull converter, control algorithm been implemented using voltage mode control. This means that output voltage measured compared reference point. difference then passed through compensator. control algorithm will look error, previous error, control history determine output value. output will determine time duty cycle. Figure provides push-pull converter control scheme.
FIGURE B-1:
PUSH-PULL CONTROL SCHEME
1:16
VREF
Voltage Error
Control Output
Duty Cycle
VOUT
1001010111 Voltage Feedback
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Figure shows MATLAB Simulink block diagram. further details each block refer MATLAB (.mdl) file.
FIGURE B-2:
MATLAB DIGITAL IMPLEMENTATION (PUSH-PULL)
VO*1 VIN1 Out1 ILOAD Product3 Expected Input Current1 Digital Control System VIN.D VIN1 Buck Modulation1 Voltage iLoad Scope1
Circuit1
Inverter Load Generator1
following bode plots generated from MATLAB (.m) file. Each plot used describe behavior system. disturbance rejection plot defined I(s) VO(s). Figure describes amount load current amplitude needed applied generate unit voltage function frequency. higher this absolute figure merit, stiffer (better) power supply will minimum which will correlate load producing 1.5V output.
FIGURE B-3:
DISTURBANCE REJECTION PLOT (PUSH-PULL)
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loop gain voltage plot shown Figure used find phase gain margin. From plot seen that phase margin (difference between degrees phase angle where gain curve crosses degrees. prevent system from being conditionally unstable, imperative that gain plot drops below when phase hits degrees. blue curve analog implementation green curve digital implementation. generally recommended have phase margin least degrees allow parameter variations. gain margin difference between gain curve where phase curve hits degrees. gain margin (where green line phase plot hits degrees)
FIGURE B-4:
LOOP GAIN VOLTAGE PLOT (PUSH-PULL)
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Figure shows closed loop bode plot. point where gain crosses degrees phase usually denoted bandwidth. this system, bandwidth voltage loop approximately 1250 (8000 rad/s), which closely matched bode plot.
FIGURE B-5:
CLOSED LOOP (PUSH-PULL)
Full-Bridge Inverter Compensator
Current mode control been implemented Inverter using control algorithms: current mode control, current well voltage measured. inverter output generated varying input voltage reference using sinusoidal lookup table. difference passed through voltage error compensator (PI) output cur-
rent reference value. measured current value subtracted from reference difference passed current error compensator (P). output compensator used control outputs. Current mode control preferred method better transient response stability output. However, current mode control usually harder implement there control algorithms instead just voltage mode control.
FIGURE B-6:
FULL-BRIDGE INVERTER CONTROL SCHEME
Voltage Error Current Reference Current Error Current Feedback 1011010011 1001010111 Voltage Feedback Control Output Output Filter Duty Cycle
Sinusoidal Reference
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Figure shows MATLAB Simulink block diagram inverter. further details each block, refer MATLAB (.mdl) file.
FIGURE B-7:
Sine Wave (input variation)
MATLAB DIGITAL IMPLEMENTATION (INVERTER)
Dtop
Dtop ILZX (2.D-1) D.VIN iLoad Circuit1 Scope2
Sine Wave VO*1
Zero-order Hold2
ILoad Digital Control System1 Out1 Out2
Full-Bridge Modulation Model1
Out1
disturbance rejection plot previously described Push-Pull section defined I(s) VO(s). inverter, minimum which implies that load amplitude 1000 (6280 rad/s), output voltage will exhibit sinusoidal variation 31V.
FIGURE B-8:
DISTURBANCE REJECTION PLOT (INVERTER)
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Figure shows loop gain bode plot inverter. From plot, seen that phase margin (difference between degrees phase angle where gain curve crosses degrees. gain margin difference between gain curve where phase curve hits degrees. plots below, gain margin (where green line phase plot hits degrees) Figure B-10 shows closed loop bode plot inverter. point where gain crosses degrees phase usually denoted bandwidth. this system, bandwidth voltage loop 1250 (8000 rad/s), which closely matched bode plots.
FIGURE B-9:
FIGURE: LOOP GAIN VOLTAGE PLOT (INVERTER)
FIGURE B-10: FIGURE: CLOSED LOOP (INVERTER)
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Scaling
gains calculated from MATLAB based real units (volts, amps, etc.). dsPIC fixed point processor values processor have linear relationship with actual physical quantities they represent. gains generated MATLAB being real units, cannot directly applied these scaled values (representation physical quantities). Therefore, consistency, these gains themselves need scaled. following sections present general concepts behind proper scaling. basic idea behind scaling quantities that need added subtracted should same scale. Scaling does affect structure control system block diagram way. Scaling only effects software representation various quantities. example, trying measure 100V. have potential divider such that 100V would give 1.65V analog pin. Then, value read format 16383 Q15(0.5), which equivalent Q15(100 200). Therefore, becomes base voltage. base normalizer) denoted other words, voltage that will produce 3.3V fullrange voltage analog pin. this point, voltage been scaled fraction software. Similarly, other physical quantities that read feedback also represented format.
GAIN SCALING
simulation control gains calculated real units. example, current mode control, output voltage loop current reference amps). Therefore, gain Amps/Volts units 1/ohms: Gain IREF goal obtain IREF appropriate format like Q15(I/IN) enable implementation current loop software. theory, voltage V/VN first multiplied then gain (G), then IREF that obtained divided current correct format. Since constants, gain scaled This value used software voltage quantity give current quantity. input quantity should fractional format (this ensured code). Then, output current quantity will automatically correct fractional quantity. This essentially solves objective scaling. same logic applies control block. considering input output units scale each block implemented software, proper scaled values arrived
SCALING FEEDBACK
properly scale gains, imperative understand feedback gain calculation. feedback represented various formats. Fractional format (Q15) very convenient representation. Fractional format allows easy migration code from design another with completely different ratings with most changes only coefficients defined header file. completely bits available processor, format most convenient allows signed operations full utilization available bits (maximum resolution). Other formats also possible, resolution lost process. allows fractional multiply operation dsPIC effectively. feedback signal (typically voltage current) usually from 10-bit ADC. Based potential divider/amplifier feedback circuitry, actual voltage currents scaled. Typically, feedback 10-bit value -1023) brought 32767 range multiplying This format also known format: Q15(m) where defined (int) 32767). These formulas will have some error need 2^15 32768, finite resolution bits only 32767. From control perspective, most systems these hardly introduce significant error. this format, +32767 corresponds +3.3V corresponds feedback circuitry left shift (x32) effectively taking physical quantity dividing larger base quantity. fractional value then represented software. goal find that larger base quantity.
SAMPLING TIME
calculation derivative integral term discrete time domain, (sampling time) factors show Since sampling time usually constant, also lumped together with gains. example, integral gain real units, scaled value.
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PRESCALER
most physical quantities represented format easy multiplication with gains, gains also need fractional format. value gain between easily represented fractional format. Multiplications then performed using fractional multiply functions like using builtin_mul functions shifting appropriately. example, (_builtin_mulss(x,y) results Q15(fx,fy), where format fractions that represented many instances, gain terms greater than unity. Since 16-bit fixed point limitation, prescaler used bring gain term within range. example, value that needs used 2.5, predivided bring within range. prescaler used term control block, also must used term control block terms added together. prevent number overflows, output output individually have properly saturated ±32767. saturation limits output must one-fourth original ±32767 account prescaler. Therefore, they ±8192. Finally after saturation, output postscaled bring proper scale again.
Modulation Duty Generation
output control system after saturation brought 0-32767. Based topology, this interpreted duty ratio/modulation index representing 0-1. This then used convert duty cycle value multiplying with period. This varies with topology, idea behind scaling same. Again, following equation used where PERIOD corresponds 100% duty Duty _builtin_mulss(m, PERIOD)
Division
output controller MATLAB model usually voltage quantity. This needs converted duty/modulation quantity. this, control output needs divided input voltage VIN. avoid division, assumed constant 1/VIN used constant multiplier bundled along with gains previous blocks.
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APPENDIX ELECTRICAL SPECIFICATIONS
This Appendix provides overview electrical specifications well scope plots from initial test results.
TABLE C-1:
Parameter VOUT fOUT VBATTERY POUT
OFFLINE REFERENCE DESIGN ELECTRICAL SPECIFICATIONS
Description Input Voltage Input Frequency Output Voltage Output Frequency Battery Input Voltage Continuous Output Power Over Load Protection Output Voltage Battery Charger Mode System Efficiency Inverter Mode System Efficiency Mains Inverter Transfer Time Inverter Mains Transfer Time Battery Charge Current Battery Input Current (note Operating Temperature Crest Factor Power Factor (Inductive Load) Power Factor (Rectifier Load) >100 1000 Units Only tested 100% load >50% load 1350 seconds Full load (resistive) Comments
tTRANSFER ICHARGE I_BATTERY Note
time will vary with output load current batteries discharge rate. Refer battery data sheet specific discharge times.
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FIGURE C-1: EFFICIENCY CHART ACROSS LOAD SPECTRUM
220V Efficiency Chart
Percentage
Load
FIGURE C-2:
OUTPUT VOLTAGE WAVEFORM LOAD
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FIGURE C-3: OUTPUT VOLTAGE OUTPUT CURRENT FULL LOAD
FIGURE C-4:
OUTPUT VOLTAGE OUTPUT CURRENT REACTIVE LOAD
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FIGURE C-5: MAINS INVERTER SWITCH OVER 400W LOAD
FIGURE C-6:
INVERTER MAINS SWITCH OVER 400W LOAD
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FIGURE C-7: DYNAMIC LOAD RESPONSE 400W UNLOAD
FIGURE C-8:
DYNAMIC LOAD RESPONSE 400W LOAD STEP
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APPENDIX
FIGURE D-1:
SCHEMATICS BOARD LAYOUT
OFFLINE REFERENCE DESIGN BOARD LAYOUT (TOP)
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FIGURE D-2:
Imax=2.5A Vmax=48V STTH8R06D 0.33e Ubat
4.7nF 1000V PGND TP13 C144 100nF R101 R103 6.8k R104 R107 6.8e 180e BAR43C PGND 47uF 100nF LM358 PGND R111 R113 R115 47nF PGND R202 R112 Iref C147 100nF 100V R110 C143 100nF R105 R106 LM358 INA168 0.68uF 100V 100uF 100V 100V
1206 390k
Ibatm+
BC817 R114
Ibatm-
OFFLINE REFERENCE DESIGN SCHEMATIC (SHEET
TOP250YN (TO220-7)
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ETD39 Flyback transformer N1:N2 52:28 Lp=700uH BC817 TP14 Zener 1SMB5941BT3G
0.22uF 630V
PGND
Charger+
1206 390k
R100 1206 390k
BYV26E
Charger-
PGND
R102 1206 390k
R108 1206 390k
R109
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FIGURE D-3:
CSPC
CSPD
/SYS_FLT
OSCO 20MHz Udcm R11712pF 12pF
Iref
RP15
RP24
PWM4L
R207 RP21 RP22 RP19 AN10 VDDCORE AN11 PWM3H PWM3L PWM2H RP16 RP29 AVSS AVDD MCLR PWM2L 100nF 10uF Tant C139 R201 DNPC140 100nF
RP20
SCLK
R127
FAULT/SD
AGND 100nFAGND C141
3V3A
R118
OFFLINE REFERENCE DESIGN SCHEMATIC (SHEET
dsVpp C142 100pF
PWM4H
FLT_CLR PGC1
RP23
R206
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4.7uH 1.5A P_FAN 100nF 10uF R116 IRLL2705 dsPIC33FJ16GS504
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dsVpp
dsICSPD
dsICSPC
ICSP galvanic isolation! connect when connected Line!
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FIGURE D-4:
R120
R119 220e
C100 100nF
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R121 R123 LED1 LED2 ICSP ICSP ICSP galvanic isolation! connect when connected ine! R124 R125 R204 R126 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN OSC2/CLKO/RA6 OSC1/CLKI RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB5/PGM RB6/PGC RB7/PGD P_BZ ICSP ICSP R128 R129 R132 R133 R134 C104 100nF R203 R135 SCLK MCLR/VPP PIC18F2420-E/SO RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT LED1 LED2
R122
C101 2.2nF
R136
7.3728MHz
R131
R13

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